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1. Introduction

About this product Product Information A survey of architectural mechanisms and implementation techniques for exploiting fine- and coarse-grained parallelism within microprocessors.

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Beginning with a review of past techniques, the mograph provides a comprehensive account of state-of-the-art techniques used in microprocessors, covering both the concepts involved and implementations in sample processors. The whole is rounded off with a thorough review of the research techniques that will lead to future microprocessors. XXXXXXX Neuer Text This mograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It presents a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and possible implementations.

The authors also provide application-oriented methods and a thorough review of the research techniques that will lead to the development of future processors.

Reading Materials

Additional Product Features Author s. Show More Show Less.

Advanced CPU Designs: Crash Course Computer Science #9

Physical Description xxii, p. Subjects Computer architecture.

Processor Architecture - From Dataflow to Superscalar and Beyond | Jurij Silc | Springer

Contents 1. Dataflow Processors 3.


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  • Processor Architecture: From Dataflow To Superscalar And Beyond by Jurij Silc.
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CISC Processors 4. Multiple-Issue Processors 5.


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Future Processors to use Fine-Grain Parallelism 6. Future Processors to use Coarse-Grain Parallelism 7.

Processor-in-Memory, Reconfigurable, and Asynchronous Processors. Notes Includes bibliographical references p. View online Borrow Buy Freely available Show 0 more links Set up My libraries How do I set up "My libraries"?

Processor Architecture: From Dataflow to Superscalar and Beyond

Monash University Library. Open to the public ; Dixson Library.

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